In the fabrication of integrated components on a semiconductor wafer or chip, narrow areas of electrical isolation are provided between device components. Recessed oxide isolation is often employed in semiconductor chips such as memory and logic chips for electrically isolating devices and regions formed on the chips.
Photolithography has been employed in constructing isolation areas of narrow width. However, the minimum resolvable line width in conventional near-UV projection photolithography is of the order or 2 to 3 microns, which provides a wider isolation area than often required for adequate electical isolation in the integrated circuits. In addition, when an exposed area of a semiconductor substrate is oxidized, there is a tendency for the oxide area to laterally expand or grow, to encompass an area of the semiconductor substrate larger than the surface area developed during the photolithographic process. This also contributes to the formation of recessed oxide isolation regions larger than required.
Integrated circuit chips characterized by smaller recessed oxide isolation regions would allow reduction in size of other chip electrical components, provide room for a larger number of active components on a single wafer and the like, all of which, among other benefits, would reduce the overall cost of the integrated circuit and reduce the minimum response times of the integrated circuit elements.
U.S. Pat. No. 4,318,759 by Trinary et al describes a complicated retro-etch process for forming narrow line widths on a semiconductor chip. First and second masking layers are required, and a retro-etched area is formed by partially retro-etching the first masking layer below the second masking layer.
U.S. Pat. No. 4,022,932 by Feng describes a process for reducing the smallest aperture dimensions in a patterned resist mask. A resist mask is placed in a chamber containing an atmosphere of resist solvent vapor which is absorbed by the mask, causing resist reflow, resulting in reduction of the dimensions of the resist openings.
U.S. Pat. No. 4,231,811 by Somekh et al describes a process for producing aligned areas of different thickness in a semiconductor chip by employing a photoresist mask having an area composed of a plurality of spaced-apart lines of predetermined width, such that the images of the lines cannot be resolved by the projection means employed. The photosensitive material receives light of intermediate intensity compared to the light associated with transparent and opaque areas of the masking member. Upon developing, areas of different thickness are formed.
U.S. Pat. No. 4,104,070 by Moritz et al describes a process for making a negative photoresist image using a positive working photoresist material containing a 1-hydroxyethyl-2-alkylimidazoline. The process of Moritz et al will be considered in greater detail in the "Detailed Description of the Invention", hereinafter. IBM Technical Disclosure Bulletins, Volume 24, No. 10, March 1982 and Volume 23, No. 5, October 1980, describe modified positive working photoresists providing, where desired, negative images on a substrate. The processes of Moritz et al and of the IBM TDB's are stated to provide better resolution and less defects than the use of other negative working photoresist materials. In addition, Moritz in an internal report not publicly available, said report being dated prior to the work of the present inventors disclosed herein but as far as known reviewed by the present inventors after they had completed their invention disclosed herein, contemplates the use of a modified image reversal process as disclosed in U.S. Pat. No. 4,104,070 with longer exposure times to form gaps on a wafer substrate narrower than the width of the opaque areas of the mask.